Hi ARM experts,
For shareability attribute, have some confusions:
1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability attribute is also set. Otherwise, how to ensure the coherence between various agents wthin shareable domain;
2 If the memory location isn't cacheable, is there any difference for a memory location with shareability or non shareability?
For shareability attribute, have some confusions: 1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability attribute is also set. Otherwise, how to ensure the coherence between various agents wthin shareable domain;
The sharability attribute tells the processor it must do whatever is necessary to allow that data to be shared. What that really means depends on the features of a particular processor.
On a processor with multi-CPU hardware cache coherency; the shareabilty attribute is a signal to engage the cache coherency logic. For example A57 can maintain cache-coherency of shareable data within the cluster and between clusters if connected via a coherent interconnect.
On a processor without hardware cache coherency, such as Cortex-A8, the only way to share the data is to push it out of the cache as you guessed. On A8 shareable, cacheable memory ends up being treated as un-cached.
Thanks a lot, Peterrielly!