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question about arbitration scheme of AHB bus matrix

JJ HUA

generate an AHB bus matrix ,using the perl script of CMSDK.

Below are the properties of the bus matrix:

  • protocol:AHB2;
  • arbitration scheme:fixed
  • 2 masters:CPU,DMA(CPU is prior to DMA)
  • 3 slaves:ROM(for instruction),SRAM(for data),sdram(other usage)
  • conectivity:full

When using Modelsim to verify,I found that if i let DMA access ROM while CPU accessing ROM to fetch instruction,there will appear a phenomenon that  CPU work normmally,but the timing of DMA AHB interface make mistakes.

I suppose that because of higher priority ,CPU works without disturbing.In contrast,DMA AHB interface goes wrong.

What above is just my thought.I want to know why.

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  • 0 in reply to Colin Campbell

    Thank you for your detailed and enlightening comments.I have tried to read the source code of Bus Matrix ,and found what i misunderstand is exactly what you point as"you have not correctly connected the HREADY signals in the system so that somewhere a transfer has been missed".

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  • 0 in reply to Colin Campbell

    Thank you for your detailed and enlightening comments.I have tried to read the source code of Bus Matrix ,and found what i misunderstand is exactly what you point as"you have not correctly connected the HREADY signals in the system so that somewhere a transfer has been missed".

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