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Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Yeo Reum Yun

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

 

Core A:

     STR R0, [Msg]

     STR R1, [Something]

Core B:

     DSB

     LDR R1 [Something] 

     ......

my questions are :

  • if Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?
  • if first question's answer is not, Should i flush the cache for writing data on memory? like DCCSW

Cuz i really really beginner, maybe that situation is wrong itself....

But, i hope your merciful answer..

Thx.

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  • 0 Arm Employee Badge in reply to Yeo Reum Yun

    Hello,

    As an aside / in addition to what Pete said, I recommend you take a look at the ARMv8-A Architecture Reference Manual's provided examples for barriers, such as in Section J7.6.1 (ARM DDI 0487A.f) shows that you should have a DMB barrier on Core A between the two stores, and a DMB barrier on Core B between the flag-checking loop and the load from the mailbox.

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  • 0 Arm Employee Badge in reply to Yeo Reum Yun

    Hello,

    As an aside / in addition to what Pete said, I recommend you take a look at the ARMv8-A Architecture Reference Manual's provided examples for barriers, such as in Section J7.6.1 (ARM DDI 0487A.f) shows that you should have a DMB barrier on Core A between the two stores, and a DMB barrier on Core B between the flag-checking loop and the load from the mailbox.

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