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Memory barrier (DSB, DMB). Does they guarantee writing data on cache to memory?

Yeo Reum Yun

Hi Experts,

I'm reading white paper for ARMv7 and ARMv8.

but when i reading cache part and memory re-ordering, i have silly questions.....

Suppose there are below instructions..

 

Core A:

     STR R0, [Msg]

     STR R1, [Something]

Core B:

     DSB

     LDR R1 [Something] 

     ......

my questions are :

  • if Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?
  • if first question's answer is not, Should i flush the cache for writing data on memory? like DCCSW

Cuz i really really beginner, maybe that situation is wrong itself....

But, i hope your merciful answer..

Thx.

Parents
  • 0
    • if Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?
      • Yes, no guarantees another core cache flush or invalidate.
    • if first question's answer is not, Should i flush the cache for writing data on memory? like DCCSW
      • DCCSW, Data Cache line Clean by Set/Way, clean to related operating core. so didn't clean to another core.

    If you want to know more information for cache coherance, read CCI specification

Reply
  • 0
    • if Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?
      • Yes, no guarantees another core cache flush or invalidate.
    • if first question's answer is not, Should i flush the cache for writing data on memory? like DCCSW
      • DCCSW, Data Cache line Clean by Set/Way, clean to related operating core. so didn't clean to another core.

    If you want to know more information for cache coherance, read CCI specification

Children
  • 0 Arm Employee Badge in reply to 박주병

    If Core A stores R1's data in its cache memory.. then does DSB guarantees R1's data also to be written on memory?

    • Yes, no guarantees another core cache flush or invalidate.

    Just to clear up any possible confusion here. A DMB does not guarantee that data is written back to main memory - it merely enforces a valid order of execution. Barrier have nothing to do with cache maintenance.