Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but
one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.
In document (ARMv7-A/R ARM Issue C) it says:
Software using an MRS (Banked register) or MSR (Banked register) instruction specifies one of these registers using a name shown in Figure B9-1, or an alternative name for SP or LR.
Software using an MRS (Banked register) or MSR (Banked register) instruction specifies one of these registers using a
name shown in Figure B9-1, or an alternative name for SP or LR.
But in both the figure and the text the names are the same: SP or LR. There is no alternative.
Yes there is a reason: I'm (still) trying to put together a standalone gdb-stub for RPi 2B (using soft breakpoints).
That "partial emulation" is needed for single stepping to figure out what the PC will be after executing an instruction.
I'm using C and inline assembly:
#define READ_REG_MODE(retvar, rg, mode) \ asm volatile (\ "mrs %[reg], r%c[rn]_" #mode "\n\t"\ :[reg] "=r" (retvar)\ :[rn]"I"(rg):\ )
#define READ_REG_MODE(retvar, rg, mode) \
asm volatile (\
"mrs %[reg], r%c[rn]_" #mode "\n\t"\
:[reg] "=r" (retvar)\
:[rn]"I"(rg):\
)
But that only works upto rg =< 12.
Had to add special code for SP and LR.
I just wondered what is the "alternative name for SP or LR".
I only found one possibility: LR_<mode> or SP_<mode>.