This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

AHB5: performing a burst transfer with HBURST=SINGLE and HTRANS=NONSEQ.

Greetings, all!

So, I have two questions about the AHB5 protocol:

(1) I see there are two ways of performing an undefined length burst transfer using AHB5 protocol:

(1.1) Set HBURST = INCR and HTRANS = { NONSEQ, SEQ, SEQ, ... }

(1.2) Set HBURST = SINGLE and HTRANS = { NONSEQ, NONSEQ, NONSEQ, ... }

Is one way more advantageous than the other? Does it make any difference, functionally and also in terms of efficiency?

(2) When using HBURST = INCR and HTRANS = { NONSEQ, SEQ, SEQ, ... }, considering that the subordinate never insert wait states but the manager is busy at some point, what is the difference of inserting HTRANS = BUSY or HTRANS = IDLE?

Thanks! :)

Parents
  • The main difference between your two "burst" examples is that 1.2 isn't a burst, it's a series of single transfers. Only 1.1 is a burst.

    So the advantage of 1.1 over 1.2 is that you are using a burst, and from a system perspective the target device might be able to respond with fewer wait states knowing that the transfers are to consecutive addresses. 1.2 is a sequence of individual transfers, so the target of these transfers does not know if the transfers are related, so might not be able to optimise transfers. For example DRAM controllers can usually perform a burst of transfers more efficiently than a sequence of single transfers.

    For 2. the difference is that an IDLE means the burst has ended and would need to restart with a NONSEQ, whereas a BUSY indicates the burst "might" continue. So again looking at the previous 1.1 answer, if the target can operate more efficiently when it sees a burst continuing, that's why BUSY would be better.

Reply
  • The main difference between your two "burst" examples is that 1.2 isn't a burst, it's a series of single transfers. Only 1.1 is a burst.

    So the advantage of 1.1 over 1.2 is that you are using a burst, and from a system perspective the target device might be able to respond with fewer wait states knowing that the transfers are to consecutive addresses. 1.2 is a sequence of individual transfers, so the target of these transfers does not know if the transfers are related, so might not be able to optimise transfers. For example DRAM controllers can usually perform a burst of transfers more efficiently than a sequence of single transfers.

    For 2. the difference is that an IDLE means the burst has ended and would need to restart with a NONSEQ, whereas a BUSY indicates the burst "might" continue. So again looking at the previous 1.1 answer, if the target can operate more efficiently when it sees a burst continuing, that's why BUSY would be better.

Children
No data