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ARM Context ID Register & Process Context Switch

onion

Hi, all

What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

Is it essential to deal with ASID if I want to make context switch correctly? Does Cortex A8 have no Context ID

Register? Minix's process context switch running on a Cortex A8 core doesn't cope with ASID when it writes

TTBR.

Thank you.

Best Regards,

Channing M.

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  • 0 in reply to onion

    Just to establish a base point.


    I see that Minix 3 has been ported to some ARM systems..

    So basically I guess Minix 3 works on ARM at the moment by flushing on context switch and I believed you wanted to use ASID to cut down on the overheads.

    However it sounds to me from what you are saying that you are porting to this board and Minix 3 is failing to run and the ASID stuff was just an idea you had about why it wasn't running.

    Is that right?

    My first guess would be that if it has been running on a different ARM system and is having problems on this one there is very possibly a memory barrier problem, for instance you need to ensure new page table entries are written away from the cache before loading the translation table base. Have you the Cortex-A Series Programmer's Guide for ARMv7-A from the ARM site? It talks a bit about this sort of thing.

Reply
  • 0 in reply to onion

    Just to establish a base point.


    I see that Minix 3 has been ported to some ARM systems..

    So basically I guess Minix 3 works on ARM at the moment by flushing on context switch and I believed you wanted to use ASID to cut down on the overheads.

    However it sounds to me from what you are saying that you are porting to this board and Minix 3 is failing to run and the ASID stuff was just an idea you had about why it wasn't running.

    Is that right?

    My first guess would be that if it has been running on a different ARM system and is having problems on this one there is very possibly a memory barrier problem, for instance you need to ensure new page table entries are written away from the cache before loading the translation table base. Have you the Cortex-A Series Programmer's Guide for ARMv7-A from the ARM site? It talks a bit about this sort of thing.

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