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ARM Context ID Register & Process Context Switch

onion

Hi, all

What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

Is it essential to deal with ASID if I want to make context switch correctly? Does Cortex A8 have no Context ID

Register? Minix's process context switch running on a Cortex A8 core doesn't cope with ASID when it writes

TTBR.

Thank you.

Best Regards,

Channing M.

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  • 0 Arm Employee Badge in reply to onion

    I suspect that it's not the TLB invalidate that is causing the problem, but rather the table walk(s) that have to happen after the invalidate.  Could you give an outline of the steps you are performing?  Also, when you say "hang" what exactly do you mean (e.g. recursive abort, or the processor can't enter debug state)?

    EDIT: Forgot an important "not"

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  • 0 Arm Employee Badge in reply to onion

    I suspect that it's not the TLB invalidate that is causing the problem, but rather the table walk(s) that have to happen after the invalidate.  Could you give an outline of the steps you are performing?  Also, when you say "hang" what exactly do you mean (e.g. recursive abort, or the processor can't enter debug state)?

    EDIT: Forgot an important "not"

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