Hi, in my current understanding, when I want to map a certain range of virtual addresses, for example 0xffff-0xffff8000, to 0x0-0x8000, I have to put the physical address in the section entry (0x0-0x8000). Now if I want to map 0xffff-0xffff8000 to 0x800-0x10000, the adresses in the section entry are 0x800-0x10000,
is that correct? Bc I have the exact same setup and although the section entry(the last block entry that points at the physical mem) address is different than then the virtual it’s address it still points to an range beginning at 0, so with zero offset…
What do I have to do to have the virtual address point to another(with an offset, of that makes sens) physical address.
Sorry, I find it really difficult to explain the problem at hand.
Best regards Niklas
Sorry for my confusing explanation. I don't want to map a region twice. I want *not* identity mapped memory....
I really only want to map 0x00000000 - 0x0000FFFF to 0x80010000 - 0x8001FFFF, so with an offset (in this case 0x8001), instead of 0x00000000 - 0x0000FFFF to 0xFFFF0000 - 0xFFFFFFFF.
Up to now I couldn't really figure out how to do that. I assumed that if I just had the section entry address point to 0x80010000 - 0x8001FFFF I would end up with my desired mapping. But that doesn't really work in my setup.
thx for you reply!
What processor do you use, what amount of memory and what type of memory? Because you can't map everything you want, part of physical addresses should be mapped directly 1-to-1 virtual to physical ones (for example memory registers of different controllers embedded on system-on-chip).
What about TTBR register, did you configure it in right way to point to your translation table?
I'm on a53 qemu dirt board with 1gb rom + 12 gb of ram.
I'm identity mapping the rom with sections(which works) and want to map the first gb of the ram to kernel address space. so 0xffff000000000000-0xffff000040000000 should be sectioned mapped to 0x40000000-0x80000000.
Therefor my section page table looks like the following.
ttbr1 base -> 0x40000000 | flags
...
0x80000000 | flags
tcr: mmu.TcrReg{ .t0sz = 16, .t1sz = 16, .tg1 = 2 })
ttbr1(and0) attr: mmu.TableEntryAttr{ .accessPerm = .only_el1_read_write, .descType = .block }
and checked numerous times with qemu wether they point to the right address...
I hope that helps