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If the mispredict happen, is there a mechanism to abort the instructions(have been fetched or decoded)?
If there is the mechanism, how does it work?
Thanks very much!
Theoretically, speculative instructions can get executed in both in-order as well as out-of-order processors as long as they are not committed (don't update/modify the processor status permanently) until the branch outcome is known. Practically, in an in-order processor speculative instructions follow the branch instructions and therefore they are never executed before the branch instruction itself is executed and actual branch outcome is known. If the branch outcome is mispredicted then speculatively fetched and decoded instructions are discarded (just ignored). In case of a misprediction there will be a few cycle delay to refill the pipeline with valid instructions (techniques like BTIC can reduce the branch misprediction penalty as you might remember from your previous post).
To support execution of speculative instructions the processor need a shadow register-file as well as a shadow store-buffer to store the temporary values until the branch is executed and the branch outcome is known.
The answer to your question is No. There is no need to have a special mechanism to flush mispeculatively fetched and decoded instructions from the pipeline. In case of a misprediction the PC is updated and new instructions are fetched. How long it takes for a processor to refill the pipeline should be clearly indicated in the user manual as it is a very important architectural feature.