Hi all
I have some problems about ahb. I have some experience with axi , but I am not familar with AHB.
Q1:Allthough AHB is old comparing with axi, it seems that ahb will not be replaced by axi. AHb is still popular. And AHB5 is released in few year ago. Comparing with axi, what is the advantage of using ahb?
Q2: why ahb's latecy is smaller than axi?
Q3: I know some arm cpu will use ahb bus or axi bus? I would like to know what reasons behind that.
Thanks a lot!
1. The advantages of using AHB-lite or AHB5 over the newer AXI protocols is mainly familiarity for some and lower pin count on interfaces or lower routing complexity.
AHB has been around longer, so designers are sometimes more familiar with it, and might have existing components with AHB style interfaces they want to reuse.
Functionally, AXI added a lot of features that AHB-lite didn't have, so things like support for security signaling and exclusive transfers, and then the newer AHB5 has added support for both of these.
But there are still features supported by AXI that are not in AHB5 such as multiple processing threads using IDs, multiple outstanding transactions, concurrent read and write transactions, so AXI is still a more richly featured protocol.
2. AHB, AHB-lite or AHB5 is not lower latency compared to AXI.
In theory both protocols can have one data transfer per clock cycle. Both are pipelined buses, with AHB having an address phase and then a data phase for each transfer, and AXI having an address channel (write and read), data channels (write and read) and a write response channel. The pipelining of these transfer phases in AHB or channels in AXI means that a burst of transfers can have one transfer in each phase of the transfer, and so one completing in each cycle.
AXI supports simple insertion of register slices on each channel to help meet timing for long paths, and these will increase latency (because they are registering), but the same is true in larger AHB based systems where you need to add AHB-AHB bridges to register paths to meet timing.
So comparing two similar sized systems you should see similar latencies.
3. The bus protocol used by any Arm CPU will likely be a decision based on a combination of the target application requirements (features required from the bus protocol, newer applications requiring cache coherency support will look at ACE or CHI), typical application bus used (micro-controllers might prefer AHB-lite for pin count or simplicity), age (older CPU designs might not have had AXI as an option).
Hope that helps...