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Is First-level table skippable? (VMSA)

Jongseok Kim

Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

How arm processor determine it? How to know first level table has only one entry????

  • 0 Arm Employee Badge

    It's similar to AArch64.  The size of the virtual space is configurable.  For example, for Hyp mode HCR.T0SZ controls the size of the address space for Hyp mode.  Where:

      size of virtual address space (in bits) = 64 - HCR.T0SZ

    In other words, as you increase the value of T0SZ you are shrinking the size of the virtual address space.

    For AArch32, when using the Long Descriptor format, each entry in the level 1 table represents one 1GB of address space.  So once you shrink the total address space to 1GB (or less), translation will start at level 2 instead.

  • 0 in reply to Martin Weidmann

    Thank you for your response, It make happy me.

  • 0 in reply to Martin Weidmann

    Martin, are your sure about AArch32? Without using the second TTBR the total address space is 4GB, where each entry in the table represents _1MB_.

    You can shrink the size of the memory described by the TTRB0 down to 32MB, but you always need a 1st level table.

  • 0 Arm Employee Badge in reply to 42Bastian

    ARMv8-A AArch32 supports two translation table formats, the short and long descriptor formats. 

    With the long descriptor format, you can have up to three levels of table:

    L1 - each entry covers 1G  (so up to 4 entries in stage 1 level 1 table)

    L2 - each entry covers 2MB (up to 512 entries)

    L3 - each entry covers 4K (always 512 entries)

    With the long descriptor format, you can have up to two levels of table:

    L1 - each entry covers 1MB (so up to 4096 entries)

    L2 - each entry covers 4K (always 256 entries)

    With the long descriptor format, you can skip level 1 if you shrink the address space to 1GB or less.  With the short descriptor format, you can still shrink the address space but you can't skip level 1).

    Note, that stage translation in AArch32 always uses the long descriptor format.

    NOTE: For ARMv7-A, only processors that implement LPAE support the long descriptor format.  That is the Cortex-A7, Cortex-A15 and Cortex-A17.