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Hello experts,
I would like to ask the reason why the exception frame forms on PSP in the Cortex-M architecture.My understanding is that MSP (Main Stack Pointer) is the interrupt stack pointer and PSP (Porcess Stack Pointer) is the normal (user) stack pointer.From my little experiences, the exception frame was formed on the interrupt stack.However, the ARM forms it on the user stack.
Best regards,Yasuhiko Kouoto.
Hello daith,
I'm sorry for late reply.
I want not to get a semantic or structural reason, but I'd like to simply know that ARM Cortex-M takes such a scheme.
Regarding the overhead, I cannot still understand without any pictures to explain it.
At the context switch, I think the registers would not get from the stack frame.
Also, I cannot understand your explanation why Cortex-A does not take such a scheme.
Best regards,
Yasuhiko Koumoto.
The overhead is pretty straightforward. This isn't exactly what happens but it illustrates the main point.
Context switch if interrupt data is stored on MSP
Timer interrupt. Interrupt data stored on MSP
Copy some registers to old process specific area
Copy interrupt data from MSP to old process specifc area
Set PSP for new process
Copy interrupt data for new process to MSP
Copy some registers from new process specific area
exit to continue new process, restore state from MSP
Context switch if interrupt data is stored on PSP
Timer interrupt Interrupt data stored on old process PSP
exit to continue new process, restore state from new process PSP
The way Cortex-M does it is just not what a person used to Linux or some other such operating system would expect. It could be simulated on Cortex-A series but it requires hardware support to work well.