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Are there differences between coprocessor instructions and instruction2:s?
I mean:
MCRR vs. MCRR2
MRRC vs. MRRC2
MCR vs. MCR2
MRC vs. MRC2
LDC vs. LDC2
STC vs STC2
I didn't find any differences in the encoding except the condition code, and no differences in the description of the functionality.
If there are no differences, are there any explanations why they are "condition-code-doubled"?
So, your idea is definitely not nonsense,but not really definitive either.
It only holds for coprocs 10 and 11.
I guess that all coproc 10 and 11 "operation writes" map to the same bit patterns as the floating point
and vector instructions - aliases,one might say.
Haven't checked anything, though (= compared fp / vector instruction encodings to coproc instruction encodings).
Another "good" question: why are coprocs 10 and 11 OK with LDC,but not with LDC2, while all other coprocs are
OK with both? Could it be some future expansion of fp/vector instructions via LDC2 only?
(I'm talking about LDC and LDC2, but the same applies for all coproc instructions:MRC/MRC2, ...)
Anyway, strange asymmetry...
Hello,
I reviewed the ARM ARM and came to the thought that cond=4'b1111 instructions (i.e. MCRR2, MRRC2, STC2. LDC2. CDP2, MCR2 and MRC2) were currently valid only for the coprocessor 10 and 11.
Therefore, you would be probably right.
Another "good" question: why are coprocs 10 and 11 OK with LDC,but not with LDC2, while all other coprocs are OK with both? Could it be some future expansion of fp/vector instructions via LDC2 only? (I'm talking about LDC and LDC2, but the same applies for all coproc instructions:MRC/MRC2, ...) Anyway, strange asymmetry...
Regarding this, I agree with you. It would be a mystery.
Best regards,
Yasuhiko Koumoto.