Hi all,
Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.
U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too. Is it possible? Can primary arm access secondary arm's registers?
Best Regards.
Srt
Wouldn't this be possible, if making connections to the device's own debug interface using GPIO pins ?
I know it might not be the most interesting way to do it, but if an external debugger can do it, I believe it should be possible to make a workaround-hack.
Interesting Idea, I might try this in the RasPi2 actually. But I wonder if we can convince somebody to implement this in real world devices.
Hi Axel,
If Core 0 has access to Core 1's memory-mapped debug registers then it is possible to halt that core, and use the DBGITR and DBGDRRTX etc. to push instructions and data through it to do this. It is a little more complex than that, but it's possible. External debug might be enacted over JTAG via something like a DSTREAM but it is exactly the same model to have another core be the debug agent. This is thanks to CoreSight being just another set of memory-mapped peripherals, and every debug transaction boiling down to a write to memory on one bus or another.
Whether each core can see the other's debug registers is totally down to the system designers, though - there's no requirement to hook up the debug APB to system space, so it may only be possible to get to this interface via the DAP.
As for seeing it in real world devices, they do exist.. unfortunately even if I could think of one right now, I don't think I could advertise it.
Ta,
Matt Sealey, Senior Applications Engineer, PEG