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A description of each of the pipeline stages / ARMv9 Cortex-A510

I am looking for a description of each of the pipeline stages for ARMv9 Cortex-A510. I haven't found more than a diagram for the pipeline. I am looking documentation on the pipeline stages.

Where can I get this documentation?

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  • There's a diagram over at wikichip.org. Depending on the details you need, a computer architecture book, or details about a510's predecessors may be sufficient.

    I guess that anyone wanting to implement the CPU does get access to the full details about the pipeline, but that must be under some sort of NDA.

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  • There's a diagram over at wikichip.org. Depending on the details you need, a computer architecture book, or details about a510's predecessors may be sufficient.

    I guess that anyone wanting to implement the CPU does get access to the full details about the pipeline, but that must be under some sort of NDA.

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