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In
ARM Cortex-A Series Programmer’s Guide for ARMv8-A: 13.2.4. Non-temporal load and store pair
it talks about a relaxation of the memory ordering requirements and then gives the example
LDR X0, [X3]
DMB NSHLD
LDNP X2, X1, [X0]
saying the memory barrier is needed otherwise it might read from an unpredictable address. I don't follow this at all,it just seems wrong to me.
"The wording in the document makes it seem like the wrong address may be used for LDNP - not the one loaded from [X3].I can't believe that is so."
It is indeed so! That is exactly what it is saying. And, in some circumstances, that is the behaviour which the programmer wants. Clearly, when using these instructions, you must be careful not to use them in ways which give undesirable behaviour.
"I really do think it is talking about address dependencies not being observed. With that as you say it could use data from [X0] from before when the load of X0 is done."
Yes, that's exactly what is is saying. Strange though it may seem!
Chris
PS - the Barrier Litmus Test document has been superseded since all of its content is now included in the ARMv8 ARM. It may not be expressed in exactly same wording but all the content has been included.
Looking at the ARMv8 ARM I see that it does describe address dependency in the way I mean in section B2.7.2 and it is consistent with the way the term is used in the Litmus test, so yes the Litmus test has been incorporated thanks.
So you are basically saying that a LDNP instruction does not even follow the basic register data dependency as described in 'Address dependencies and order' in that section? I am afraid, I think you have somehow got the wrong end of the stick somewhere as I think this type behavior is completely broken. The two things you said yes to above are different - address dependencies are not the same as register data dependencies, the first was a register data dependency and the second was an address dependency.