Using an Arm Cortex M4. We've noticed that when a certain function triggers our RTC interrupt, we get a usage fault interrupt instead.
After some debugging and sifting through registers, we noticed that our RTC vector address is 0x46 and our usage fault vector is 0x06. We're thinking something may be masking the 0x40 off.
For builds that have the usage fault (and this is key), We've confirmed that triggering an RTC interrupt causes the usage fault interrupt to fire. Also from inside the usage fault, I change PC to the start of the RTC handler, I see normal operation. This seems to confirm that for some reason the IRQ service is jumping into the vector table incorrectly.
Another odd thing, if we see this issue, and just add some random lines of code that do nothing, the fault goes away. At first we thought this was resolved per this IAR article:
https://www.iar.com/knowledge/support/technical-notes/general/unexpected-usagefault-or-hardfault-exceptions
Basically compile with --no_unaligned_access...but that proved to not resolve the problem.
Just curious if others have seen this problem, or any ideas how to resolve this.
From the ARM ARM:
The Vector table must be naturally aligned to a power of two whose alignment value is greater than or equal to (Number of Exceptions supported x 4), with a minimum alignment of 128 bytes.
> this is a setting from the manufacturer of the chip
How/where? I checked out a couple of ARMs I work with, and didn't actually see any alignment details for VTOR contents, other than the ones derived from the core_cm4.h file from ARM (which doesn't take into account any implementation-defined interrupts.)
I use the Silabs Gecko. It's part of the startup_[chip].c file for the __vector_table[]