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For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the access attribute, say, the transcation table mark MEM_A as non-cachebale/non-bufferrable? Or if its SMMU_CBn_SCTLR's M bit is 0?
Thanks a lot for reply, peterriely. I saw MMU in A53 TRM, so what's default version of this 'MMU', it is just a instance of SMMU?
Sort of, but not really.
The processor MMU and SMMU do basically the same job - address translation. They also use the same translation table formats, and have most of the same settings. However, they aren't identical. For example, the processor MMU doesn't have the multiple contexts of a SMMU.
Another difference is who does the programming. For the processor MMU, it is software running on the processor itself. For SMMUs, the master behind the SMMU would rarely program the SMMU and would probably be prevented from doing so. Instead again it's software running on the apps processor.