Architectures and Processors forum no C bit in SMMU_CBn_SCTLR

State Accepted Answer
Locked Locked
Replies 2 replies
Subscribers 349 subscribers
Views 4537 views
Users 0 members are here

Options

Related

How was your experience today?

This discussion has been locked.

You can no longer post new replies to this discussion. If you have a question you can start a new discussion

no C bit in SMMU_CBn_SCTLR

Jerry over 10 years ago

I am reading SMMU spec V2.0, and wondering why no C bit in SMMU_CBn_SCTLR. There is M bit in it.

Parents

0 Martin Weidmann over 10 years ago

The SCTLR.C bit in the ARM architecture enables the data and unified caches. The SMMU does not include data/unified caches. Any caching would be done by a separate cache block, which would have it's own enables.
Cancel
Vote up 0 Vote down

Cancel

Reply

0 Martin Weidmann over 10 years ago

The SCTLR.C bit in the ARM architecture enables the data and unified caches. The SMMU does not include data/unified caches. Any caching would be done by a separate cache block, which would have it's own enables.
Cancel
Vote up 0 Vote down

Cancel

Children

0 Jerry over 10 years ago in reply to Martin Weidmann

Thanks a lot, Martin.
Cancel
Vote up 0 Vote down

Cancel