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1/ WHY "the width of the ID field at a slave interface is wider than the ID field at a master
interface"??? Can you please explain in more detail the reason???
2/ Do AXI protocol have support "read interleaving"???
Thanks you so much!
It's common to prefix the AXI ID from the masters with a master ID.
Take a simple example, with two masters A and B. Each master has a 2-bit AXI ID. The interconnect "expands" the AXI ID to 3 bits, with bit[3] signifying which master the transaction came from. Say b1xx is master A, and b0xx is master B.
For a real word example, here is how the NIC-400 uses IDs:
ARM CoreLink NIC-400 Network Interconnect Technical Reference Manual: 2.3.12. Global ID and ID reduction
(NOTE: Remember that masters such as a processor connect to the interconnect's slave interfaces)
Interestingly, the multi-core processors do something similar internally. Taking the example of the Cortex-A9 MPCore, the originating core is encoded within the AXI ID the processor presents to the interconnect:
Cortex-A9 MPCore Technical Reference Manual: 2.3.3. AXI transaction IDs
Thank you for your help!