We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hello everyone,
Please describe me the transfer continuation process after ERROR response from the slave.
As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer then how can it?
Does it need to insert SEQUENTIAL transfer for the continuation of the current transfer or it has to insert IDLE transfer then NONSEQUENTIAL transfer to complete the current transfer?
Regards,
Vishal
Thanks Yasuhiko,
The conclusion regarding "the MASTER changing the address during the second cycle of ERROR response to continue the current transfer" ; I thought it from the specification sheet named "AMBA® 3 AHB-Lite Protocol Specification (ARM IHI 0033A)" (Page No 3-10). Here I have mentioned it :
Slave error responseIf a slave provides an ERROR response then the master can cancel the remaining transfers in the burst. However, this is not a strict requirement and it is also acceptable for the master to continue the remaining transfers in the burst.
You can see the bold statement : "However, this is not a strict requirement and it is also acceptable for the master to continue the remaining transfers in the burst."
But in the specification it is not explained through detailed diagram ; hence I thought regarding the continuation of the burst and posted it on the forum to check whether it is appropriate or not.
Of course I got the correct understanding and endorsement from your side ; thanks for that.