We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Thanks,
Sujatha.
Hi,
Do you have any news about the availability of this guide for ARMv7-A ( Cortex A53) , with the number of cycles for each instruction?
I have to compare this theoretical number with the one I found reading the "Cycle Counter Register", so I can validate the value I am reading. Fast response will be appreciated.
Thank you in advance,
Larissa
Just read Chris' answer, the "theory" might not match the real life, as the cycle counts in a core manual do not reflect bus interactions.If you do not trust the performance counters, use another "time base", for example a timer in the SoC.