Cortex-R5 processor has an ACP interface that consisted by ACP master interface and ACP slave interface. When there is an DMA equipment in my system, the data coherency between L1 and L2 memory system will be corrupted. In order to solve this problem, how to use the ACP interface? how should ACP interface be connected?
ACP slave connects with DMA master interface, and ACP master interface connects with memory system? why？ how does the ACP interface solve the data coherency problem?
Cortex-R5 processor有一个ACP接口，分为ACP master interface和ACP slave interface。当系统中有DMA器件时，由于DMA在数据搬移的过程，可能会破坏数据一致性。所以使用R5的ACP接口，这个应该和哪里进行连接呢。
看了ARM的文档，我的理解是，ACP slave接口和DMA的master接口相连，ACP master接口和memory system相连。
请问一下，这个ACP master和memory system相连，应该怎么连？ACP实现一致性的原理是什么？能否介绍一下思想？