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I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.
I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could notice that the SDR i.e SDRAM is not accessible.
I have enabled MMU in such a way that PA=VA.
There is no issue if I copy less amount data.
And also, If I disable D-Cache then there is no abort and it works fine. But I would like to enable D-Cache for faster access.
Thanks and regards,
Gopu
Hello Gopu,
you should clear C bit in the CP15 Control Register c1 before initializing L2 Cache.
Secondary, you should invalidate L2 Cache by similar method to L1 Cache.
These two steps are lost.
Finally, you should set C bit in the CP15 Control Register c1.
For your reference, The below are L2 Cache enable/disable sequences extracted from "Cortex™-A8 Technical Reference Manual Revision: r3p2".
8.3 Enabling and disabling the L2 cache controller To enable the L2 cache following a reset or to change the settings of the L2 Cache Auxiliary Control Register, you must use the following sequence: 1. Complete the processor reset sequence or disable the L2 cache.2. Program the L2 Cache Auxiliary Control Register. See c9, L2 Cache Auxiliary Control Register on page 3-95 for details. NoteIf you have configured the processor to support parity or ECC memory, you must enable those features before you can program the C bit. MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register MCR p15, 1, <Rd>, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register 3. Program the Auxiliary Control Register to set the L2EN bit to 1. See c1, Auxiliary Control Register on page 3-47 for details. MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register 4. Program the C bit in the CP15 Control Register c1. See c1, Control Register on page 3-44 for details. MRC p15, 0, <Rd>, c1, c0, 0 ; Read Control Register MCR p15, 0, <Rd>, c1, c0, 0 ; Write Control Register To disable the L2 cache, but leave the L1 data cache enabled, use the following sequence:1. Disable the C bit.2. Clean and invalidate the L1 and L2 caches.3. Disable the L2 cache by clearing the L2EN bit to 0.4. Enable the C bit.NoteTo keep memory coherent when using cache maintenance operations, you must follow the L2 cache disabling sequence. Cache maintenance operations have an effect on the L1 and L2 caches when they are disabled. A cache maintenance operation can evict a cache line from the L1 data cache. If the L2EN bit is set to 1, the evicted cache line can be allocated to the L2 cache. If the L2EN bit is not set to 1, then evictions from the L1 data cache are sent directly to external memory using the AXI interface.
8.3 Enabling and disabling the L2 cache controller
To enable the L2 cache following a reset or to change the settings of the L2 Cache Auxiliary Control Register, you must use the following sequence:
1. Complete the processor reset sequence or disable the L2 cache.2. Program the L2 Cache Auxiliary Control Register. See c9, L2 Cache Auxiliary Control Register on page 3-95 for details.
NoteIf you have configured the processor to support parity or ECC memory, you must enable those features before you can program the C bit.
MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register MCR p15, 1, <Rd>, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register
3. Program the Auxiliary Control Register to set the L2EN bit to 1. See c1, Auxiliary Control Register on page 3-47 for details.
MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register
4. Program the C bit in the CP15 Control Register c1. See c1, Control Register on page 3-44 for details.
MRC p15, 0, <Rd>, c1, c0, 0 ; Read Control Register MCR p15, 0, <Rd>, c1, c0, 0 ; Write Control Register
To disable the L2 cache, but leave the L1 data cache enabled, use the following sequence:1. Disable the C bit.2. Clean and invalidate the L1 and L2 caches.3. Disable the L2 cache by clearing the L2EN bit to 0.4. Enable the C bit.NoteTo keep memory coherent when using cache maintenance operations, you must follow the L2 cache disabling sequence. Cache maintenance operations have an effect on the L1 and L2 caches when they are disabled. A cache maintenance operation can evict a cache line from the L1 data cache. If the L2EN bit is set to 1, the evicted cache line can be allocated to the L2 cache. If the L2EN bit is not set to 1, then evictions from the L1 data cache are sent directly to external memory using the AXI interface.
Best regards,
Yasuhiko Koumoto.