Hello all,
I am confusing by SysTick interrupt behavior.
Even if SysTick clock was processor clock, the processor woke up from Sleep or DeepSleep mode by SysTick interrupt.
My understanding is that the processor clock will stop during WFI execution (i.e. Sleep or DeepSleep).
I think that SysTick cannot count during WFI execution.
Could anyone teach me why SysTick can work during Sleep or DeepSleep mode?
Joseph Yiu answered for my post Clock gating of Cortex-M Deeep Sleep mode that NVIC and SysTick will be clocked in Sleep mode.
However he answered that all clocks will stop in DeepSleep mode.
I confirmed that SysTick did not stop during DeepSleep mode by the experiment of FRDM-KL25Z board which equips Cortex-M0+.
SysTick timer was operational even in DeepSleep mode on FRDM-KL25Z board.
Is SysTick timer exclusive (i.e. no clock gating)?
Thank you and best regards,
Yasuhiko Koumoto.
Hello Matt,how about "Devices Generic User Guide"? Isn't it the authorized or official document?I referred the below statements from "Cortex-M0/M0+ Devices Generic User Guide" at the previous thread.
When the WIC is enabled and the processor enters deep sleep mode, the power management unit in the system can power down most of the Cortex-M0 processor. This has the side effect of stopping the SysTick timer.
Do you say these statements are the implementation matters?
I wonder there are spaces which can be modified by vendors for the NVIC or SysTick which is a part of CPU core. Or does the CPU core have an exclusive STCLK input pin?
Of course, I have already asked the question to Freescale. A Freescale person is currently denying the fact the SysTick will wake up the device from Deep Sleep mode because HCLK should stop during Deep Sleep mode.
To solved the issue, I have already provided the sample code which will reproduce the fact. However, I have not yet received any responces.I am very confusing now.
Best regards,Yasuhiko Koumoto.
The phrasing "the power management unit in the system can power down most of the Cortex-M0 processor" suggests that it isn't necessary to power it down, and implementations may or may not take that opportunity.
The details you want are in the Cortex-M0+ or Cortex-M4 Integration Guide which is available to licensees of the Cortex-M IP in question, and I don't think is suitable discussion on such a public forum.
Needless to say, it isn't something designers are forced to implement on a design, and there are many, many options..
Hello Matt,
OK, I understood what you said although my purpose had not been accomplished.
I would like to close this post.
Thank you for your patient answer.
Best regards,
I have gotten the official answer from Freescale AE team.
They are as followings.
It’s not very clear in the manual, but the systick is actually clocked by the platform clock which is the same frequency as the core clock. We don’t really document the difference between the two very well. Since they are the same frequency most of the time it doesn’t matter, but for low power modes it starts to become important. The platform clock runs in WAIT mode, so it is expected operation for the systick to run in WAIT mode and be able to wake you up. I think the platform clock still be available in STOP mode too, not the BUS clock and this clock's never mentioned in the RM yet.
It’s not very clear in the manual, but the systick is actually clocked by the platform clock which is the same frequency as the core clock. We don’t really document the difference between the two very well. Since they are the same frequency most of the time it doesn’t matter, but for low power modes it starts to become important. The platform clock runs in WAIT mode, so it is expected operation for the systick to run in WAIT mode and be able to wake you up.
I think the platform clock still be available in STOP mode too, not the BUS clock and this clock's never mentioned in the RM yet.
As the results, it was implementation matter.
However, I have been very much surprised.
I would like to share it with the community.