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SWD cannot read/write MEM-AP

DHuynh

Hi,

I try to use SWD protocol connect with ARM Cortex-M0.

The first step I read IDCODE register:

  • Send more than 50 SWCLKTCK cycles with SWDIOTMS=1. This ensures that both SWD and JTAG are in their reset states.    
  • Send the 16-bit JTAG-to-SWD select sequence on SWDIOTMS. Write 0x79E7.    
  • Send more than  50 SWCLKTCK cycles with SWDIOTMS=1. This ensures that if SWJ-DP was already in SWD mode, before sending the select sequence, the SWD goes to line reset.   
  • Perform a READID to validate that SWJ-DP has switched to SWD operation.

I can read it. IDCODE=0x0BB11477.

The second step I set CDBGRSTREQ and CDBGRSTACK (bits 28 and 29) in the CTRL/STAT (address 0x4) register of the DP.

But when I try to read IDR register, it's only answer 0x00. The right answer is 0x04770021. I don't know what I'm missing?!

Please help me fix its!! Thanks you very much!

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