Please let me know about different between "block entry" and "table entry" in VMSAv8-64 Translation table

A Block entry maps the virtual address space covered by the table entry to some physical memory.

The different levels of translation table break memory into different sized blocks.  It's probably easier to understand with an example:

48-bit virtual address space, 4KB translation granule ( * )

The starting level of translation is level 0.  Each entry in this table covers 512GB of address space.  Each entry in our level 0 table will either:

• Fault (all accesses to these address range trigger an abort), or
• Table (pointer to level 1 table).

A level 1 table sub-divides the 512GB covered by the L0 table entry.  Each level 1 table entry covers 1GB of address space (so 512 entries in the table as a whole).  Each entry in the table will be one of:

• Fault
• Table (pointer to level 2 table this time)
• Block

Block entries map the virtual address space covered by the table entry (1GB in this case) to a physical address.

A level 2 table sub-divides the 1GB covered by the L1 table entry.  Each level 2 table entry covers 2MB of address space (so 512 entries in the table, as before).  As with the L1 table, each entry can be a Fault, Table (pointer to L3 table) or a Block.

A level 3 tables sub-divides the 2MB covered by a L2 table entry.  Each level 3 table entry covers 4KB of address space, so again 512 entries in total.  Each entry can be a Fault or a Page (equivalent to Block at L1 and L2).  You can't subdivide further, hence no Table entries.

Tables become something of a trade off.  It is generally more efficient to use map using larger blocks - as you need fewer levels of table and a TLB entry will cover more space.  But smaller blocks are more flexible.

(* 48 bits is the maximum size supported, it can be configured to be smaller.  As the virtual address space shrinks, or larger granule sizes are used, fewer levels of translation are needed).

A Block entry maps the virtual address space covered by the table entry to some physical memory.

The different levels of translation table break memory into different sized blocks.  It's probably easier to understand with an example:

48-bit virtual address space, 4KB translation granule ( * )

The starting level of translation is level 0.  Each entry in this table covers 512GB of address space.  Each entry in our level 0 table will either:

• Fault (all accesses to these address range trigger an abort), or
• Table (pointer to level 1 table).

A level 1 table sub-divides the 512GB covered by the L0 table entry.  Each level 1 table entry covers 1GB of address space (so 512 entries in the table as a whole).  Each entry in the table will be one of:

• Fault
• Table (pointer to level 2 table this time)
• Block

Block entries map the virtual address space covered by the table entry (1GB in this case) to a physical address.

A level 2 table sub-divides the 1GB covered by the L1 table entry.  Each level 2 table entry covers 2MB of address space (so 512 entries in the table, as before).  As with the L1 table, each entry can be a Fault, Table (pointer to L3 table) or a Block.

A level 3 tables sub-divides the 2MB covered by a L2 table entry.  Each level 3 table entry covers 4KB of address space, so again 512 entries in total.  Each entry can be a Fault or a Page (equivalent to Block at L1 and L2).  You can't subdivide further, hence no Table entries.

Tables become something of a trade off.  It is generally more efficient to use map using larger blocks - as you need fewer levels of table and a TLB entry will cover more space.  But smaller blocks are more flexible.

(* 48 bits is the maximum size supported, it can be configured to be smaller.  As the virtual address space shrinks, or larger granule sizes are used, fewer levels of translation are needed).

Thank for your detail response.

ARM VMSA can reduce "page table walk" from block descriptor, I can map large amount of memory to one-block descriptor, instead map serveral page descriptor repeatedly.

Is it correct?