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some question about ACE

digital_kevin

Hi all:

I'm reading ACE protocol. I have some questions about such scenario:

two cache masters (master 0/1) and main meomry are connected by Coherent interconnect.

master 0 and master 1 are both SharedClean.

cacheline size : 64bytes.

Q1: if master 1 writes to portion of the shareable cacheline（update the 1st byte of cacheline）,

result 1: master 1 will issue CleanUnique and ,  master 1 cache state become UniqueDirty.

result 2 :master 1 cache state become SharedDirty, master 0 cache state will still be SharedClean.

which result will be right?

Q2: if result 2 in Q1 is right and then master 0 updates the 3rd byte of cacheline,  how the 2 masters and interconnect act?

 

Thanks.

Parents
  • 0 Arm Employee Badge

    Hi ,

    I think in your scenario master 1 will issue a CleanUnique transaction and master 0 will receive a CleanInvalid snoop request.The result is your result 1, with the cache line in master 0's cache becoming invalid.

    M1: SC -> UD

    M0: SC -> I

    The result 2 you describe with master 1 ending up with a different copy of the line in its cache compared to master 0 is not possible: with ACE, all dirty copies of a line in all caches must be the same at all times.

    See also this discussion and this whitepaper.

Reply
  • 0 Arm Employee Badge

    Hi ,

    I think in your scenario master 1 will issue a CleanUnique transaction and master 0 will receive a CleanInvalid snoop request.The result is your result 1, with the cache line in master 0's cache becoming invalid.

    M1: SC -> UD

    M0: SC -> I

    The result 2 you describe with master 1 ending up with a different copy of the line in its cache compared to master 0 is not possible: with ACE, all dirty copies of a line in all caches must be the same at all times.

    See also this discussion and this whitepaper.

Children
  • 0 in reply to vstehle

    Hi vstehle,

    Thanks for the replay.

    I have read the whitepaper. It seems that I didn't have a good understanding of SharedDirty state.

    Could you build a scenario to describe when the state changes to SharedDirty ?

    Really appreciate your help!

  • +1 Arm Employee Badge in reply to digital_kevin

    An example scenario could be: master 0 has a dirty line, master 1 does not have the line and issues a ReadShared transaction, the interconnect will snoop master 0, master 0 will transfer data to master 1.

    M0: UD -> SD

    M1: I -> SC

    Master 0 could also pass dirty to master 1:

    M0: UD -> SC

    M1: I -> SD

    See the AMBA AXI and ACE Protocol Specification for all the state transitions.

    Note that not all implementations are able to handle SharedDirty. This is the reason why there is a ReadNotSharedDirty transaction to avoid the second scenario for example.