Is it legal to execute SVC from EL1 in ARMv8?
I have two cores in the same A53, and both are configured the same way with respect to system registers and MMU. When executing SVC #1 from EL1(S), one of the cores correctly generates syndrome 0x56000001 in ESR_EL1 (EC 0b01010101: "SVC instruction execution in AArch64 state"), but the other core generates syndrome 0x02000000 (EC 0b000000: "reason unknown").
Because of your question, I did try swapping addresses, but did not find it to make a difference.
But I do see that in D1.12.4 ("Synchronous exception prioritization for exceptions taken to AArch64 state") of the Armv8-A architecture reference manual, various interrupt types have different priorities. That makes me suspect that something is causing a higher priority exception than my SVC, on every single instruction, and consequently obscuring the ESR_EL1 syndrome.
At present I'm looking disfavorably on the debugger, because I can clear out ESR_EL1, but as soon as I do any stepping, ESR_EL1 immediately goes back to 0x02000000, even though no exception is taken as far as I can tell. I don't know enough about the debugger to know whether that is plausible.