We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
Hi Experts,
How to derive the cache memory requirement for the working of the software ?
I could understand that each of the A/M/R processors have its own applications and build with its own Cache size MPU/MMU configurations but how this is derived with the metrics ?
For example, How to decide the amount of cache size required for the working software with some practical metrics ?
Like depends on the Cache Miss/Hit ratio, Code text/data/bss size, etc.
How it could be derived or solved ?
Considering the latency and bandwidth as ideal, is there any way to derive the cache and its performance impact with the system performance ?
If you had ideal bandwidth (infinite) and latency (zero) then you wouldn't need a cache. The entire point of caches is to work around the non-ideal parts of real systems.
Or else it would be great if I can get some general thumb rule or recommendations in the usage of cache memory.
In general "more is better", but memories are large so increase silicon area / cost. There are plenty of good articles online about writing good cache-friendly algorithms - none of that is ARM specific.
HTH, Pete
Hi Peter,
Fine I am able to see it now.
At last one thing, How ARM decides the cache size for each of the processor type (A/R/M) which is being released ?
It will be based on Cost/Speed or any other metrics ?
Regards,
Techguyz
How ARM decides the cache size for each of the processor type (A/R/M) which is being released ?
In the general case we don't - most ARM core L2 caches (which is where most of the area goes) are configurable, so we leave this as a choice to our partners to choose the appropriate balance of area, performance, and power for their target market - there isn't one "right answer".
Thanks peter for all these lightening