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I want to know which instruction is Mops？which is uops?
How to understand it？
assemble code ==> machine code ==>Mops ==> uops
cortex-A78 support 4Insts/6Mops, it means IF unite can fetch 4 insts and 6Mops, without decode,where did Mops come from?
in the 2.1 pipeline overview
Instruction are first fetched ad then decode into internal Macro-ops.
int the picture. L1 Icache cache line is 64Byte, why the rate is 16Byte/cycle？
DANNYWW said:int the picture. L1 Icache cache line is 64Byte, why the rate is 16Byte/cycle？
Because it is the way it is designed.What is your actual intention behind these questions?
Instructions are firstly fetched from external memory to instruction cache, and pipeline does pre-decode to MOP，and places MOPs to MOP cache.
Instruction cache line size is not necessarily the same as number of instructions of decoder.
Thinking about most of armv8-a CPUs (A53, A57, A73...) cache line size are all 64 Byte.
Sharing the same cache line size makes coherency easier to implementation across different system, and software more portable in case Cache Line Size alignment is required.
which Instructions is insts, which is Mops
Hi DANNYWW,
I think that as per Zenon (Zhilong) Xiu 's answer, instructions (insts) have not been decoded yet, and MOPs are what you obtain after decoding the instructions. Logically speaking they are very close and the distinction is more a matter of representation inside the processor.
The µops are different; quoting the Arm Cortex-A78 Core Software Optimization Guide:
"A MOP can be split into two Micro-OPerations (μOPs) further down the pipeline after the decode stage."
For example:
"Stores μOPs are split into address and data μOPs."
thanks very much