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Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.
Register slice is described in AMBA 3.0 AXI.
"This makes possible a trade-off between cycles of latency and maximum frequency of operation."
"It is also possible to use register slices at almost any point within a given interconnect."
As you can see the first picture, register slices are located between masters and interconnect, between slaves and interconnect.
(this is a picture that i refer to any PPT about AMBA 3.0 axi.)
My questions,
Firstly, does Register slice mean the buffer???
I think that operation frequency can be increased because of operating pipelining behavior.
Secondly, where register slices is correctly located??? in masters? in the interconnect? in slaves?
I carefully guess that register slices can be located in the masters and slaves.
Because user can not modify the interconnect.
Thirdly, if i insert the register slices, where i have to design the register slices.
I want to know register slices in detail.