Hello,
I am trying to raise L3 SLV interrupts of the ARM PL310 L2 cache controller by generating an AXI slave error on a L2C slave peripheral (which is not DDRC). On my Xilinx Zynq SoC, the ARM PL310 revision is r3p2.
Here is the current status:
The AXI slave error is correctly propagated from the L2C's M1 master port back to to the L2C's slave port, and then back to the CPU's AXI master port such that a data abort exception is raised.
However, the interrupt is not set in either Interrupt Pending Register (IPR) or Interrupt Status Register (ISR) of the L2C.
I did not find any required configuration of the ARM PL310's L2C to enable reporting of these interrupts... I am relying on this information to handle CPU exceptions with fine grain. So it is important for me to get these interrupts to be notified, and any help would be welcome.
Thank you.
Regards,
Florian
According to TRM of PrimeCell® Level 2 Cache Controller(PL310):
"The response is attached to the returned data. The AXI read channel returns a response for every transfer of data returned. In the case of an error returned for a Read Allocate line fill, the line is not loaded into the data RAM, the tag RAM is not updated, and the corresponding SLVERRINTR or DECERRINTR interrupt line is raised."
and from Table 2-20 of the same TRM:
"Access type: Noncacheable read transactions and non-bufferable write transactions"
"Error response mechanism: Error response is precise and is passed back to the processor using a read response on the slave port read channel or the write response channel."
So from my understanding non-cacheable strongly ordered accesses to slave peripherals by L2CC do not raise an exception in L2CC. That's really a pitty....
Please let me know if my understanding is correct.Thanks.