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Additional memory cycles during LDR with unaligned address

When LDR makes an unaligned memory access on a Cortex-M4 (ARMv7), I would expect there to be two memory read cycles required to retrieve the data. More specifically, I would expect that to be true whether the address is off by 1, 2, or 3 bytes. However, I've measured the execution time (of a long sequence of LDR's) and found that the time for the "off by 2" case is about 25% faster than either the "off by 1" or "off by 3" cases. Does this mean that the retrieval requires 2 read cycles for off by2, but three for off by 1 and off by 3?

Dan

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