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ARMv8 Secure EL1 problem

Steven Meng

Hi, arm experts,

We want to use ARCH32 mode in secure EL1, I see some descriptions in ARMv8 Arch Reference Manual about Secure EL1 ARCH32 mode as follows:

One is the VBAR(secure), it is mapped to  VBAR_EL3, the other is SCTLR (secure), it is mapped to SCTLR_EL3.

That means secure EL1 and EL3 share VBAR and SCTLR?

 

Moreover, in SCTLR ARCH32 mode (G4.2.114 in ARMv8 Reference Manual), write M(bit 0) only means EL1 and EL0 stage 1 address translation enabled,

If EL1 and EL3 share SCTLR, how can I config it in ARCH32 mode?

That really confuse me,  wait for your help, thank you!

Steven

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  • 0 Arm Employee Badge in reply to Martin Weidmann

    Should have added....

    In Monitor mode, the SCR.NS bit is only controlling which copy of a banked register is accessed when you read/write it.  It does _not_ change which one affects current execution.  For example, it is SCTLR(S).M which controls whether the MMU is enabled for the Secure state (which Monitor mode is part of) regardless of the SCR.NS bit value.

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  • 0 Arm Employee Badge in reply to Martin Weidmann

    Should have added....

    In Monitor mode, the SCR.NS bit is only controlling which copy of a banked register is accessed when you read/write it.  It does _not_ change which one affects current execution.  For example, it is SCTLR(S).M which controls whether the MMU is enabled for the Secure state (which Monitor mode is part of) regardless of the SCR.NS bit value.

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  • 0 in reply to Martin Weidmann

    Thanks for you quick reply, Martin!

    I just noticed that there is no EL1(S) in "

    EL0(NS)   EL0(S)  EL1(NS)  EL2(NS)  EL3(SCR.NS=1)  EL3(SCR.NS=0)

       -             -             -             -                -                           RW

    "

    So definitely all registers can be accessed with the same mode defined in armv7 specification in this case, just as you said.  I understand now.

    In addition, I have another question as below, could you help me about it?

    To use AArch32 EL3, I know that AA64nAA32 pin can be configued as 0. My question is, if AA64nAA32 is configured as 1 when processor power up, i.e, system runs in AArch64 EL3 mode, and in this mode, if I use SPSR_EL3 to switch system to 32bit monitor mode, can we say that system will run in 32bit EL3 mode?

  • 0 Arm Employee Badge in reply to geekfolk

    moonlight wrote:

    My question is, if AA64nAA32 is configured as 1 when processor power up, i.e, system runs in AArch64 EL3 mode, and in this mode, if I use SPSR_EL3 to switch system to 32bit monitor mode, can we say that system will run in 32bit EL3 mode?

    Short answer, no - it'd be treated as an illegal exception return.

    The execution state of the highest implement EL (*) can only change on a reset. 

    More generally, execution state (AArch32/AArch64) can only change on an EL change.  An exception return from AArch64 EL3 to AArch32 Monitor mode isn't a change in EL (they're both EL3) - therefore there can't be a change in execution state anyway.

    This also applies to the other ELs.  So let's say you were in EL1 as AArch64, you can't do an exception return into one of the AArch32 EL1 modes.  It would also be an illegal exception return.

    To change the execution state of an EL you need, therefore, to be in a higher.  So to change EL1 from using AArch32 to AArch64 (or vice verse) you'd need to be in EL2 or EL3.

    (* EL3 and EL2 are optional.)