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Hello all,
I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .
The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.
On Reset, the CPU 0 jumps to the Flash ROM 0 and the boot loader stored in the Flash ROM 0 executes and do the minimal enough
H/W settings and then release the CPU 1 core from the reset status. CPU 0 core then transfer the "user program 0" to the SDRAM and CPU 1 core is responsible for transferring the "user program 1" to the SDRAM in the memory location of different address ranges.
The expectation is, CPU 0 is taking control of transferring the User program 0 to the SDRAM and jumps over there and CPU 1 is taking control of transferring the User Program 1 to the SDRAM at different address location. Now, in the SDRAM memory there are two "User programs" running. I assume that I need to tweak some MMU settings to achieve this. But not able to find the pin-pointed information in the documents or I am not referring the right guides.
Please see the attached image which briefs the architecture and the requirement of my client. If possible, I want to restrict the
CPU 0 s ability to view the memory region of CPU 1 and vice versa.
CPU 0 controls User Progam 0 in the SDRAM memory and able to access only the defined memory region
CPU 1 controls User Progam 1 in the SDRAM memory and able to access only the defined memory region
Which document has the relevant information to understand the details I require? Any hints?
Regards
Senthil
Hello skrajago.
on what issue do you feel difficulties? I think your intention is quite usual procedures.
Best regards,
Yasuhiko Koumoto.
Hello Yasuhiko,
Thanks for the response. Are you saying that in a dual core architecture, this can be achieved without any specific settings in the MMU block or some settings in the SDRAM controller?
If that is so, then I am not concerned. In this case, how do we control the access permission of the memory region for the individual CPU cores?
Hi skrajago,
there would be many things to be considered and I cannot say all.
First of all, CPU0 and CPU1 must share the same address map.
Can you show me the address map?
Especially I would like to know the address map of boot area (i.e. around address 0).
How are the two flash ROMs seen by both CPUIs?