MMU table management during CPU mode switch

Hello,

I have been working on developing comprehensive Data Abort and Prefetch Abort handlers for our ARM Cortex A9 dual-core CPU.

Among the exceptions which are covered by these handlers, I am now trying to develop the part related to DDR ECC uncorrectable errors. Such an error actually results in an AXI slave error on the AXI read bus, which in turn triggers a Data Abort and in particular an asynchronous external memory abort. In this case the Fault Status bits of the Data Fault Status Register (DFSR) are equal to 0x16 (in short descriptor format).

When such an exception occurs, I would like to further check whether the DDR ECC uncorrectable error is due to 2 stuck bits, 1 stuck bit or only 2 flip bits. The mitigation won't the same in the 3 cases.

For this purpose I have to comply with the following procedure:

1. Disable DDR ECC and single bit error scrubbing;

2. Write all 1's

3. Read and check if there are bits stuck at 0; if so I count them as stuck bits.

4. Write all 0's;

5. Read and check there are bits stuck at 1; if so I count them as stuck bits and add the result to the stuck-at-0 stuck bits.

6. Enable DDR ECC and single bit error scrubbing.

When I perform this sequence inside the Data Abort handler, in Abort mode, I end up with a MMU translation fault before I have finished doing it. 

So I am a bit confused. I don't see why my MMU table has been corrupted...

1) My bare metal application runs in CPU system mode. The Data Abort handler runs in CPU Abort mode. The general purpose registers {r0-r3,r12,lr} are saved and restored when switching from one mode to the other. But the same MMU table is used right?

2) My MMU table address is set in TTBR0. I don't use TTBR1. From my understanding TTBR1 is used for pages shared accross processes such a OS kernel. Shall I used TTBR1 for page table instead of TTBR0?

3) all caches are disabled during my application execution. So even though I let the TTBR0's IRGN and RGN bits as write-back write-allocate the MMU is not supposed to be evicted and written back to DDR from any of the cache...in other words there shall be no write transaction to the MMU table section in DDR...

I would really appreciate if anyone has any hint on this issue.

Thank you.

Florian