Hi,
Can anyone tell me if it is possible to test L1/L2 cache for Cortex A55?
In the spec, L1 cache can be directly accessed in EL3. However, I hope I can do some memory test for the L1/L2 cache in EL1.
Is there a way to do that and how?
Thanks,
-Zhiping Jiang
直接运行“ldr x0,[x0]\n”,x0是size_t型数组，元素是相对于起始地址的偏移地址，然后设置不同的x0数组大小，就能看到时间在l1和l2大小会有个时间变化，虽然不能精确的计算两个内存的尺寸大小，但可以直观的感受到。
Thank you, Sujun.
But what I want to do is to verify the L1/L2 cache like to verify any other memory parts. In other words, I hope I can write some pattern, say all '0' or 'F' to the cache and read back and compare to see if there is any difference (failure).
So far, I can be sure that we can do this in EL3 for L1. But I didn't see any post for L2 cache.