Hi,
I would like to debug my SoC with CortexA-53 core from the reset vector.
For this, I am writing the EDECR.RCE bit and does a warm reset.The core is getting reset and halt at reset vector. The status is also found to be correct from the EDSCR register.But i Am not able to properly debug the core afterwards. Ican read and write the registers. But cannot do the step operation.Do I need to do any other initialization for this?
Regards,Ranjith
Michael Williams
Reset Catch and Halting Step are in the same set of debug events, so if you are correctly halting on a Reset Catch there should be no additional initialization for Halting Step. I would suggest also checking what the EDESR and DBGAUTHSTATUS registers show. It might be as Bastian suggests that something is removing authentication.