From the ARMv8 spec, section K11.6 there is a discussion of the issues that arise from normal memory being weakly ordered. It's clear that without a DMB in both parts of the code, P2 can see either the old value at [R1] or the new value. Leaving that aside I have a question about store reordering.
P1: STR R5, [R1] STR R0, [R2] P2: WAIT([R2]==1) LDR R5, [R1]
Say that an IRQ/FIQ occurs on P1, could it be the case that the interrupt arrives after the value has been commit to [R2] but before the value has been commit to [R1]?
If so, would the core have to ensure that the first store completes before taking the interrupt so that there is no consistency violation, or is there no such guarantee and the ELR will return us to the first store in program order, causing us to store to [R2] twice?
If an interrupt modifies the same memory location as a foreground process you need to use exclusive access. For this they are made.