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System wide cache flush

M. Elsayed Badawy

Hello,

I'm working with i.MX8DX (Dual Core CortexA35 + CortexM4) with the following simplified caching system:

My need is to flush a cached memory area to RAM in order to be viewed by the M4 core, unfortunately this area maybe cached by Core 0 and Core 1, something like this:

If Core 0 "only" did execute the assembly instruction (DC CIVAC) on address X for lines equal to size Y, on both L1 and L2, will the data cached by Core 1 also be cleaned and invalidated to RAM?

If not, do I need to execute (DC CIVAC) on both Core0 and Core1? Or there is another system-wide call that can be executed on Core 0 only to do the job?

Also, how can I test a behavior like this? Any advice?

Thanks in Advance.

Parents Reply Children
  • 0 in reply to Norbert Goldstein

    Thank you for your reply, the link is for ARMv7, but it really helped.

    I did find the following link:
    developer.arm.com/.../cache-coherency

    It states the following:

    "... This means that software on one core can issue a cache clean or invalidate operation to an address that might currently be stored in the data cache of a different core that holds the address.... "

    It states also that the instruction "DC CIVAC" is broadcasted.

    The question is now, do I need to clean and invalidate L1 and L2 for the address range? Or cleaning and invalidating L2 only will do the job?

  • 0 in reply to M. Elsayed Badawy

    I'm not using this, so I don't know the details.
    This behavior/procedure must be defined in the documentation of your device.
    If broadcast Cache Maintenance Operations supported for L1+L2 caches, then you need only use these operations.
    If broadcast Cache Maintenance Operations supported only for L1 caches (I think this is what is supported), then you should use a similar procedure as described at ARMv7 (see attached image - Clean Operation flow, check if you have this procedure in your Device documentation).