Cortex A53 Bare metal booting have FIQ exception. How to debug?

Hi

I study coresight test with cortex A53 CPU.

I get FIQ interrupt when I running helloworld test in ini_libc function. But I don't known why.

I use gcc-linaro 4.9 toolchain : aarch64-none-elf-gcc  with glibc 2.14

Set CPU config pin aa64naa32 to 1.

Do I miss something? 

-----------------------------------------------------here is example boot code----------

mov x0, xzr
mov x1, xzr
mov x2, xzr
mov x3, xzr
mov x4, xzr
mov x5, xzr
mov x6, xzr
mov x7, xzr
mov x8, xzr
mov x9, xzr
mov x10, xzr
mov x11, xzr
mov x12, xzr
mov x14, xzr
mov x15, xzr
mov x16, xzr
mov x17, xzr
mov x18, xzr
mov x19, xzr
mov x20, xzr
mov x21, xzr
mov x22, xzr
mov x23, xzr
mov x24, xzr
mov x25, xzr
mov x26, xzr
mov x27, xzr
mov x28, xzr
mov x29, xzr
mov x30, xzr

// Zero the stack pointers, link registers and status registers

mov sp, x0
msr sp_el0, x0
msr sp_el1, x0
msr sp_el2, x0
msr elr_el1, x0
msr elr_el2, x0
msr elr_el3, x0
msr spsr_el1, x0
msr spsr_el2, x0
msr spsr_el3, x0

// Initialise vector base address register for EL3
adr x1, vector_table
msr vbar_el3, x1

// -----------------------------------------------------------------------------
// Variable definitions
// -----------------------------------------------------------------------------

// Values to set I and F bits in cpsr register
//.equ I_BIT , 0x80
//.equ F_BIT , 0x40
// Values for different modes in cpsr register
//.equ MODE_IRQ , 0x12
//.equ MODE_ABT , 0x17
//.equ MODE_UND , 0x1b
//.equ MODE_SYS , 0x1f

// -----------------------------------------------------------------------------
// Initialise stack pointers
// -----------------------------------------------------------------------------

// Use CPU No to calculate stack pointer
adr x1, stack_top
mrs x2, mpidr_el1
and x2, x2, #0xFF // x2 == CPU number
mov x3, #CPU_STACK_SIZE
mul x3, x2, x3

mrs x2, mpidr_el1
and x2, x2, #0xFF00
asr x2, x2, #8 // x2 == Cluster number
mov x4, #(CLUSTER_STACK_SIZE)
mul x2, x4, x2 // 4stack_size x clusternum
add x3, x3, x2 // add 4 X cluster num x stack size

sub x1, x1, x3
mov sp, x1

// Ensure all writes to system registers have taken place
dsb sy
isb sy

// Enable interrupts
msr DAIFClr, #0xF
// Configure FIQ to be taken at EL3 by setting SCR.FIQ.
// This allows a FIQ to wake CPUs that wait in WFI in EL3
// at the end of the boot code.
mrs x0, scr_el3
orr x0, x0, #(1<<2)// FIQ bit
orr x0, x0, #(1<<1)// IRQ bit
msr scr_el3, x0

// -----------------------------------------------------------------------------
// Start the test
// -----------------------------------------------------------------------------
cpu_start:
// SelectCPU is run first so that only the selected CPU will run initialisation.
// The cpu selection could instead be done here to fit the requirements of specific systems
// For gcc we need to call init_libc to handle initialisation of c librarys etc before starting main
// Once main has returned _exit will finish the simulation using the function specified in gcc_retarget.c
bl SelectCPU
bl init_libc
bl main
b _exit

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simulation message

ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loaded snapshot worklib.cortexa53_intkit_tb:v
ncsim> run
cxdt.bin
( 21825ns ) CPU0: Unexpected exception: curr_el_spx_fiq
( 29005ns ) CPU0: ** TEST FAILED**
CPU0 terminated the test at 29865ns (2986 cycles)
Simulation complete via $finish(1) at time 29865 NS + 1

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