Hi：
I have an idea that A15 and R7 are located on different AXI buses to build two systems respectively. In order to be more flexible, I hope to connect the two systems so that they can access each other. But the AXI MASTER ID bit width depends on the SLAVE ID bit width and the number of SLAVE interfaces. After the access loop is formed, the ID bit width will conflict. How can I solve this problem?
thank you very much!
What you would need to do is look at the IDs that could appear at each of the slave ports coming out of one interconnect into the next and see if you can reduce the width by finding bits that remain static or are always the same as other bits (or always the inverse of other bits, or some other logical combination).
If we look at the top interconnect, the width=8 slave port going down to the bottom interconnect cannot be accessed by the width=6 master port coming up from the bottom interconnect (because that would result in circular address decoding paths), so that reduces the number of possible ID combinations and increases the possibility that "redundant" ID bits can be identified. So by looking at all the possible ID combinations that the slave port CAN see, you can usually reduce the ID width required, so not using some of the ID output bits and tying off some of the ID inputs.
Depending on what AXI interconnect design you are using, you might find some already have an option to try to reduce the number of ID bits generated.
However if this still does not result in sufficient ID bit savings, you could try rebuilding the interconnect by connecting up the master ports to internal switches in a different order in the hope that different internal "routing" ID bits are assigned, hopefully then allowing better ID width reduction using the above methods.
But if none of that works, your only option would be to design some sort of ID compression logic, and that isn't going to be easy, so please try to manually identify bits in the ID encodings that can be removed first.