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I'm confused when I see the description of L1 cache:
L1 data memory system:The L1 data cache is organized as a Virtually Indexed, Physically Tagged (VIPT) cache.
*Note*In the L1 data memory subsystems, aliases are handled in hardware and from the programmer's point of view, the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations) and a 16-way set associative PIPT cache (for 64KB configurations).
Few materials are about this mechanism, could someone kind offer me some ideas?
Thanks and have a nice day! :)
Why? Because ARM did add some hardware and the that's the result.Actually, I do not see the reason for the question, as it says"from the programmer's point of view".