How to use L2 cache as memory from ACP access on zynq Cortex A9 ?

Hi,

I'm a FPGA designer and this new project is challenging for me because it has to deal with ACP port and L2 Cache of the ARM core of the Zynq FPGA device !

So it's new and I guess will need some touchy software, so any help, advice or C examples would be great !

What I need to do is :

- Periodically the PL part has to store using the ACP port a fixed amount of data at a fixed address in the L2 cache provided by software

- Each time the data has been updated in the L2 cache the software will get the data to use them.

- The L2 cache is supposed to be the "storage memory" and so, if possible, I don't want to have the physical cachable memory associated to this !  (If really needed I can create a "phantom" address section in the PL, meaning I can response to the AXI access but without the physical memory)

Context:

- No DDR available,

- Single core Zynq Cortex A9 device,

- Software executes from OCM

For now I have the following information :

- (Zynq TRM ) ACP coherent write requests: An ACP write request is coherent when AWUSER[0] = 1 and AWCACHE[1] =1 alongside AWVALID. In this case, the SCU enforces coherency. When the data is present in one of the Cortex-A9 processors, the data is first cleaned and invalidated from the relevant CPU. When the data is not present in any of the Cortex-A9 processors, or when it has been cleaned and invalidated, the write request is issued on one of the SCU AXI master ports, along with all corresponding AXI parameters with the exception of the locked attribute. 

Note: The transaction can optionally allocate into the L2 cache if the write parameters are set accordingly.

=> What I understand is that :

    - The Data will be written in both the L2 cache and onto the destination to the physical memory, because of SCU coherency ? Or coherency only means the SCU will update the cache status for the associated line ?

   - if yes does this means I have to use an allocate definition with AwCACHE value with write-allocate to have the data also written in L2 cache  ?

   - I can eliminate the physical update step if I use the lock attribute, => meaning using ACP AwLock signal ? meaning software locking of the associated L2 cache section ?

Questions :

- In the software how do I "request" the storage room in the L2 cache ?

- In the software how do I get the address in the L2 cache where the ACP is supposed to write ?

- In the software what are the configuration actions do I have to do to use the L2 cache in the mode ?

As you can see for now it's pretty confused for me, so any help woud be very great !

Many thanks in advance.