axi ordering

The AXI spec tried to simplify itself in that it only describes a point-to-point connection between a master and a slave. How you then build an interconnect to connect multiple masters to multiple slaves is left up to you, the idea being that it gives you a lot of flexibility in how you might do this, and all the interconnect needs to ensure is that any protocol requirements are met at its external ports.

So you will have external AXI masters connected to AXI slave interfaces on the interconnect (where the interconnect needs to ensure all AXI slave protocol requirements are met), and then you will have AXI master interfaces on the interconnect connected to external AXI slaves (where the interconnect then needs to meet any AXI master protocol requirements are met).

Q1. As above, the AXI spec doesn't describe rules for within the interconnect, only at the AXI slave and master interfaces on that interconnect. So if the interconnect was routing transactions to two different slaves, those slaves could complete those transfers in a different order than the original master required, but the interconnect logic then needs to re-order those transaction completions if the protocol requires it (for transactions using the same ID).

Q2. Same direction here means reads or writes. Read and write operations are performed with no ordering requirements between them (other than for exclusive sequences), so the spec is stating that a series of write transactions using the same ID will complete in the order they were issued, or a series of read transactions using the same ID will complete in the order they were issued.

Q3. Overlapping addresses. An AXI transaction states a start address, a number of transfers, and by how much each transfer increments on the last one (unless it is a FIXED burst), so taken together these 3 controls gives you a range of byte addresses being accessed. So you could have 2 separate transactions, with different start address, length and width values, which have byte addresses that appear in both ranges, so "overlapping".

Q4. Hopefully answered above, "masterA" connects to "portA" on your interconnect, and this "portA" will be an AXI slave.

Yes, it can be confusing about thinking what components have master ports and which have slave ports, so just think that in a chain of components, the upstream interface on each point-to-point connection in the chain is a master port and the downstream interface is a slave port.

So perhaps you have an AXI master connected via an AXI-AXI bridge for timing purposes, then maybe an AXI downsizer to reduce the data width from 64 bits to 32 bits, and then an interconnect, through maybe another AXI-AXI bridge and finally an AXI slave, at each step you have an AXI master interface driving an AXI slave interface. The AXI master connects to an AXI slave port on the AXI-AXI bridge, then an AXI master port on the AXI-AXI bridge drives an AXI slave port on the AXI downsizer, then an AXI master port on the downsizer drives an AXI slave port on the interconnect, and so on down the chain of connected components.

The AXI spec tried to simplify itself in that it only describes a point-to-point connection between a master and a slave. How you then build an interconnect to connect multiple masters to multiple slaves is left up to you, the idea being that it gives you a lot of flexibility in how you might do this, and all the interconnect needs to ensure is that any protocol requirements are met at its external ports.

So you will have external AXI masters connected to AXI slave interfaces on the interconnect (where the interconnect needs to ensure all AXI slave protocol requirements are met), and then you will have AXI master interfaces on the interconnect connected to external AXI slaves (where the interconnect then needs to meet any AXI master protocol requirements are met).

Q1. As above, the AXI spec doesn't describe rules for within the interconnect, only at the AXI slave and master interfaces on that interconnect. So if the interconnect was routing transactions to two different slaves, those slaves could complete those transfers in a different order than the original master required, but the interconnect logic then needs to re-order those transaction completions if the protocol requires it (for transactions using the same ID).

Q2. Same direction here means reads or writes. Read and write operations are performed with no ordering requirements between them (other than for exclusive sequences), so the spec is stating that a series of write transactions using the same ID will complete in the order they were issued, or a series of read transactions using the same ID will complete in the order they were issued.

Q3. Overlapping addresses. An AXI transaction states a start address, a number of transfers, and by how much each transfer increments on the last one (unless it is a FIXED burst), so taken together these 3 controls gives you a range of byte addresses being accessed. So you could have 2 separate transactions, with different start address, length and width values, which have byte addresses that appear in both ranges, so "overlapping".

Q4. Hopefully answered above, "masterA" connects to "portA" on your interconnect, and this "portA" will be an AXI slave.

Yes, it can be confusing about thinking what components have master ports and which have slave ports, so just think that in a chain of components, the upstream interface on each point-to-point connection in the chain is a master port and the downstream interface is a slave port.

So perhaps you have an AXI master connected via an AXI-AXI bridge for timing purposes, then maybe an AXI downsizer to reduce the data width from 64 bits to 32 bits, and then an interconnect, through maybe another AXI-AXI bridge and finally an AXI slave, at each step you have an AXI master interface driving an AXI slave interface. The AXI master connects to an AXI slave port on the AXI-AXI bridge, then an AXI master port on the AXI-AXI bridge drives an AXI slave port on the AXI downsizer, then an AXI master port on the downsizer drives an AXI slave port on the interconnect, and so on down the chain of connected components.