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Cortex-A8 performance

rlepage

I'm working an a project on a Texas Instruments AM3517 Cortex-A8 processor. I was seeing less than expected performance, and did a simple comparison with a Cortex-M3 processor. The M3 performance was more than twice as good as the A8(?!).

The test was a simple count to 100,000:

while (1)
{
    volatile uint32_t    i;
  
    dbg_PinSet(DBG_PIN_00);
    for ( i = 0; i < 100000; i++ )
    {
    }
    dbg_PinClear(DBG_PIN_00);
}

This is a bare metal system.  Timing was measured with a scope and the debug pin, and found to be about 40 ms on the A8 clocked at 600 MHz, and about 14 ms on the M3 clocked at 72 MHz.

The code on the A8 is running from the on chip 64K ram to remove cache and external memory effects.  Interrupts are disabled on both processors.

I'm relatively new to the A8, and suspect I'm missing something simple in setup somewhere.

Any pointers or help will be greatly appreciated.

Thanks,

-Rob

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  • 0

    Did you turn on the MMU, caches, and branch predictor? (The caches are virtually indexed, so you will need the page tables set up and the MMU enabled before you can turn the caches on, so it takes a little work to get this going).

    > The code on the A8 is running from the on chip 64K ram to remove cache


    This does not remove the need for cache. Cache is generally single cycle access, the on chip RAM is hanging off an internal AXI slave somewhere inside the chip, so will be 20-30 cycles to access (vs > 100 cycles for external DDR). All Cortex-A cores are designed to run with caches turned on, no sane use case will run with them disabled - it will cripple performance.

    HTH,
    Pete

Reply
  • 0

    Did you turn on the MMU, caches, and branch predictor? (The caches are virtually indexed, so you will need the page tables set up and the MMU enabled before you can turn the caches on, so it takes a little work to get this going).

    > The code on the A8 is running from the on chip 64K ram to remove cache


    This does not remove the need for cache. Cache is generally single cycle access, the on chip RAM is hanging off an internal AXI slave somewhere inside the chip, so will be 20-30 cycles to access (vs > 100 cycles for external DDR). All Cortex-A cores are designed to run with caches turned on, no sane use case will run with them disabled - it will cripple performance.

    HTH,
    Pete

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