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Hello,
I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4).
Currently, I use Load/Store executive assembly instructions along with memory attributes for the MMU to synchronize between the CortexA cores.
My question is, is there a similar technique to synchronize between the A35 cores and the M4 core? Or this is a vendor specific mechanism that shall be used (NXP in our case)?
Thank you.
LDREX/STREX will not work. But IIRC you can use the "Messaging Unit".