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Hello Guys,
I connected the peripheral (LED) with cortex-M0 processor and APB BUS using CMSDK in FPGA of the spartan 6 family. I used the AHB-APB bridge to connect it to the processor. I am attaching the peripheral in the code section. I wrote startup code in assembly. The address of LED is 0x40000000. I was trying to send multiple values in peripheral using a loop.
I see the expected values in the LED in behavioral simulation in Xilinx ISE. But When I run post route simulation only the first value is sent to the LED and other values do not appear in LED. When I implemented in the FPGA I don't see multiple values assigned to the LED. Only the first value is assigned just like post route simulation. I am stuck here for almost a month but could not get to solve it. Is there any design guideline that I am missing in the peripheral that I need to follow?
-------------------------this is verilog file of APB-LED----- module APB2LED( //AHBLITE INTERFACE //Global Signal input wire PCLK, input wire PRESETn, //Slave Select Signals input wire PSEL, //Address, Control & Write Data input wire PREADY, input wire [11:0] PADDR, input wire PWRITE, input wire PENABLE, input wire [31:0] PWDATA, input wire PSLVERR, // Transfer Response & Read Data output wire [31:0] PRDATA, //LED Output output wire [7:0] PLED ); //signals wire read_enable_LED; wire write_enable_LED; wire write_enable_LED_01; //Address Phase Sampling Registers reg [7:0] pLED; assign read_enable_LED = PSEL & (~PWRITE); // assert for whole APB read transfer assign write_enable_LED = PSEL & (~PENABLE) & PWRITE; // assert for 1st cycle of write transfer assign write_enable_LED_01 = write_enable_LED & (PADDR[11:2] == 10'h000); //Data Phase data transfer always @(posedge PCLK or negedge PRESETn) begin if(!PRESETn) pLED <= 8'b0000_0000; else if(write_enable_LED_01) pLED <= PWDATA[7:0]; end //Transfer Response assign PREADY = 1'b1; //PREADY = 1 assign PSLVERR = 1'b0; //PREADY = 0 //Read Data assign PRDATA = (read_enable_LED) ? {24'b0,pLED} : {32{1'b0}}; assign PLED = pLED; endmodule
Hi Andy Neil, Thanks for the reply.